Memory Management Strategies

ITCS 343 Opera-ng System Principles Memory Management Strategies Virtualizing Resources †¢? Physical Reality: Di? erent Processes/Threads share the same hardware –? Need to mul-plex CPU (Just ?nished: scheduling) –? Need to mul-plex use of Memory (Today) –? Need to mul-plex disk and devices (later in term) –? The complete working state of a process and/or kernel is de? ned by its data in memory (and registers) –? Consequently, cannot just let di? erent threads of control use the same memory –? Probably don’t want di? erent threads to even have access to each other’s memory (protec-on) †¢?Physics: two di? erent pieces of data cannot occupy the same loca-ons in memory †¢? Why worry about memory sharing? Memory Hierarchy of a Modern Computer System †¢? Take advantage of the principle of locality to: –? Present as much memory as in the cheapest technology –? Provide access at speed o? ered by the fa stest technology Processor Control Second Level Cache (SRAM) Main Memory (DRAM) Secondary Storage (Disk) Tertiary Storage (Tape) On-Chip Cache Registers 1s 100s Datapath Speed (ns): Size (bytes): 10s- ­? 100s Ks- ­? Ms 100s Ms 10,000,000s 10,000,000,000s (10s ms) (10s sec) Gs Ts Background ? Program must be brought (from disk) into memory and placed within a process for it to be run †¢? CPU can access directly to registers and main memory –? Register access in one CPU clock (or less) –? Main memory can take many cycles †¢? Cache sits between main memory and CPU registers - ­? to reduce CPU idle .me and make the available data faster to access. †¢? Protec-on of memory ensures correct opera-on –? to protect the opera. ng system from access by user processes and, –? to protect user processes from one another. –? One simple implementa. on is through base and limit registers Mul– ­? stepProcessing of a Program for Execu-on †¢? Prepara-on of a program for execu-on involves components at: †¢? Addresses can be bound to ?nal values anywhere in this path †¢? Dynamic Libraries –? Compile -me (i. e. â€Å"gcc†) –? Link/Load -me (unix â€Å"ld† does link) –? Execu-on -me (e. g. dynamic libs) –? Depends on hardware support –? Also depends on opera-ng system –? Linking postponed un-l execu-on –? Small piece of code, stub, used to locate the appropriate memory- ­? resident library rou-ne –? Stub replaces itself with the address of the rou-ne, and executes rou-ne Mul– ­? step Processing of a Program or Execu-on †¢? User programs go through several steps before being able to run. †¢? This mul– ­? step processing of the program invokes †¢? The appropriate u-lity (the rectangle) †¢? Generates the required module at each step (the circle) †¢? Basically, it is all about bind – addres s mapping. Binding of Instruc9ons and Data to Memory †¢? Address binding of instruc-ons and data to memory addresses can happen at three di? erent stages –? Compile 9me: If memory loca-on known a priori, absolute code can be generated; must recompile code if star-ng loca-on changes –? Load 9me: Must generate relocatable ode if memory loca-on is not known at compile -me –? Execu9on 9me: Binding delayed un-l run -me if the process can be moved during its execu-on from one memory segment to another. Need hardware support for address maps (e. g. , base and limit registers) †¢? Controlled overlap: †¢? Address Type: –? Separate state of threads should not collide in physical memory. Obviously, unexpected overlap causes chaos! –? Conversely, would like the ability to overlap when desired (for communica-on) –? A physical (absolute) address is a physical loca-on in main memory. –? A logical (virtual) address is a eference to a m emory loca-on that is independent of the physical organiza-on of memory. –? All memory references in user process are logical addresses. –? A rela-ve address is an example of logical address in which the address is expressed as a loca-on rela-ve to some known point in the program (ex: the beginning address). †¢? Transla-on: †¢? Protec-on: –? Ability to translate accesses from one address space (virtual) to a di? erent one (physical) –? When transla-on exists, processor uses virtual addresses, physical memory uses physical addresses –? Side e? ects: Can be used to avoid overlap,Can be used to give uniform view of memory to programs –? Prevent access to private memory of other processes †¢? Di? erent pages of memory can be given special behavior (Read Only, Invisible to user programs, etc). †¢? Kernel data protected from User programs †¢? Programs protected from themselves Base and Limit Registers †¢? Each process has a separate memory space (logical/user address space). †¢? A pair of base and limit registers de? ne the logical address space –? base register holds the smallest legal physical address –? limit register speci? es the size of the range of a process †¢? Could se base/limit for dynamic address transla9on (oBen called â€Å"segmenta9on†): –? Alter address of every load/store by adding â€Å"base† –? User allowed to read/write within segment  »? Accesses are rela9ve to segment so don’t have to be relocated when program moved to di? erent segment –? User may have mul9ple segments available (e. g x86)  »? Loads and stores include segment ID in opcode: x86 Example: mov [es:bx],ax.  »? Opera9ng system moves around segment base pointers as necessary Mul-programming †¢? Problem: Run mul-ple applica-ons in such a way that they are protected from one another †¢? Goals: –?Isolate processes and kernel fro m one another –? Allow ?exible transla-on that: †¢? Doesn’t lead to fragmenta-on †¢? Allows easy sharing between processes †¢? Allows only part of process to be resident in physical memory †¢? (Some of the required) Hardware Mechanisms: –? General Address Transla-on –? Dual Mode Opera-on †¢? Flexible: Can ?t physical chunks of memory into arbitrary places in users address space †¢? Not limited to small number of segments †¢? Think of this as providing a large number (thousands) of ?xed- ­? sized segments (called â€Å"pages†) †¢? Protec-on base involving kernel/user dis-nc-on